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MICRF405
290MHz - 980MHz ISM Band ASK / FSK Transmitter
General Description
The MICRF405 is a 290MHz-980MHz RF transmitter IC designed for unlicensed ISM band operations. It's designed to work in the North American 315MHz and 915MHz bands as well as the European 433MHz and 868MHz bands. The device is fully FCC Part 15.247 and EN300-220-compliant. The transmitter consists of a FSK/ASK modulator, PLL frequency synthesizer and a power amplifier. The frequency synthesizer consists of a voltagecontrolled oscillator (VCO), a crystal oscillator, dual modulus prescaler, programmable frequency dividers and a phase-detector. The loop-filter can be internal or external. The output power of the power amplifier can be programmed to eight levels. A lock detect circuit detects when the PLL is in lock. In FSK mode, the user can select between three different modulation types allowing a data rate up to 200kbps. When selecting FSK modulation applied with dividers, the MICRF405 is switching between to sets of register values (M0,N0,A0:"0" and M1,N1 and A1:"1"). The second modulation type is closed loop VCO modulation using the internal modulator that applies the modulated data to the VCO. The third FSK modulation type is Open loop VCO modulation. In ASK modulation, the user can select between two modulation types, with or without spreading. In both modes the modulation depth is programmable.
RadioWire
(R)
Features
* * * * * * * * * * FSK/ASK transmitter Frequency programmable ASK modulation depth programmable High efficiency power amplifier Programmable output power Power down function MCU reference clock Base band package engine TX buffer No external tuning circuitry
Applications
* * * * * * Meter reading Automotive Smart Home Remote control systems Residential Automation Wireless security system
MicroLead Frame and MLF are registered trademarks of Amkor Technologies RadioWire is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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Table of Contents
General Description ................................................................................................................................................................... 1 Features ..................................................................................................................................................................................... 1 Applications................................................................................................................................................................................ 1 Table of Contents....................................................................................................................................................................... 2 Ordering Information .................................................................................................................................................................. 3 Block Diagram............................................................................................................................................................................ 3 Pin Configuration........................................................................................................................................................................ 4 (1) Absolute Maximum Ratings ..................................................................................................................................................... 5 (2) Operating Ratings ................................................................................................................................................................... 5 Electrical Characteristics ............................................................................................................................................................ 5 Electrical Characteristics (cont.)................................................................................................................................................. 6 Data and Configuration Interface ............................................................................................................................................... 7 Programming Interface Timing .............................................................................................................................................. 8 Writing to the Control Registers in MICRF405....................................................................................................................... 9 What to write: ........................................................................................................................................................................ 9 How to write:.......................................................................................................................................................................... 9 The two different ways to "program the chip" are: ................................................................................................................. 9 Writing to a Single Register ................................................................................................................................................... 9 How to write:.......................................................................................................................................................................... 9 Writing to All Registers ........................................................................................................................................................ 10 What to write ....................................................................................................................................................................... 10 How to write:........................................................................................................................................................................ 10 Writing to n Registers Having Incremental Addresses......................................................................................................... 10 What to write ....................................................................................................................................................................... 11 Writing to n Registers Having Non-Incremental Addresses................................................................................................. 12 Reading from the Control Registers in MICRF405 .............................................................................................................. 12 Reading from the Interrupt Register .................................................................................................................................... 12 Data Interface and Data Transfer............................................................................................................................................. 13 Packet Engine Overview: .................................................................................................................................................... 14 How to transmit a Packet with the Packet Engine: .............................................................................................................. 15 Programming Summary....................................................................................................................................................... 17 Main Modes of Operation ......................................................................................................................................................... 18 Power Amplifier ........................................................................................................................................................................ 18 Frequency Synthesizer............................................................................................................................................................. 19 Crystal Oscillator (XCO) ........................................................................................................................................................... 21 VCO ......................................................................................................................................................................................... 22 Charge Pump and PLL Filter.................................................................................................................................................... 24 Modulation................................................................................................................................................................................ 27 Bit rate settings.................................................................................................................................................................... 30 Modulator ............................................................................................................................................................................ 30 Deviation setting.................................................................................................................................................................. 31 Shaping ............................................................................................................................................................................... 31 Modulator saturation............................................................................................................................................................ 31 Lock Detect ......................................................................................................................................................................... 32 Low Dropout Regulator (LDO) and Low Battery Detector.................................................................................................... 33 Bit Description .......................................................................................................................................................................... 34 Typical Application Circuit ........................................................................................................................................................ 42 Package Information ................................................................................................................................................................ 45
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Ordering Information
Part Number MICRF405YML Junction Temp. Range -40 to +125C
(1)
Package PB-Free 24-Pin MLF
(R)
____________________________________________________________________________________________________
Block Diagram
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Pin Configuration
24-Pin MLF(R) (Top View) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name VDD RFGND RFVDD RFOUT RFGND NC XTB XTA DVDD DGND VDD LD CLKOUT RDY/DATACLK DATAIN SCK SIO SEN SRV CPOUT VARIN AGND AVDD CIBIAS HEATSINK O O O O I I I/O I O O I O I O Type Pin Function VDD RF Ground RF VDD RF output RF Ground Not connected Crystal oscillator output Crystal oscillator input Digital VDD Digital ground VDD Lock Detect output Programmable Clock output Transmit buffer Ready / Alternative Data clock Alternative Data input SPI clock Serial input/output Serial programming interface enable Service interrupt pin Charge pump output VCO varactor input Analog ground Analog VDD Bias Ground
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Absolute Maximum Ratings(1)
Supply Voltage (VDD)......................................... +3.7V (3) Voltage on any pin (GND = 0V). .. -0.3V to 3.7V Lead Temperature (soldering, 20sec.)............. 260C Storage Temperature (Ts) ................ -55C to +150C (4) ESD Rating All pins except pin 4...................................... 2 kV Pin 4 (RFOUT)............................................ 200 V
Operating Ratings(2)
Supply voltage (VIN)............................ +2.2V to +3.6V RF Frequencies.......................... 290MHz to 980MHz Data Rate (NRZ) ...........................................200kbps Ambient Temperature (TA) .............. -40C to +125C Package Thermal Resistance (R) MLF (JA) ............................................41.7C/W
Electrical Characteristics
fRF = 915MHz. VDD = 3.0V; TA = 25C, bold values indicate -40C< TA < +125C, unless noted.
Parameter RF Frequency Operating Range Power Supply Power Down Current Standby Current PLL mode current VCO and PLL Section Reference Frequency 1kHz loop filter bandwidth, Fphd=200kHz PLL startup 3kHz loop filter bandwidth, Fphd=500kHz 30kHz loop filter bandwidth, Fphd=1000kHz Standby-TX (PA on) 30kHz bandwidth Crystal Oscillator Start-Up Time Charge Pump Current Transmit Section Output Power Output Power Tolerance RLOAD = 250, Pa2-0=111 RLOAD = 250, Pa2-0=001 Over temperature range Over power supply range RLOAD = 150, PA2-0=111 Tx Current Consumption RLOAD = 150, PA2-0=001 RLOAD = 150, PA2-0=000 Modulation depth ASK/OOK Binary FSK Frequency Deviation Data Rate
(5) (5)
Condition Freq_band=0 Freq_band=1 Freq_band=2-3
Min 290 430 860 2.2
Typ
Max 325 490 980 3.6
Units MHz MHz MHz V A A mA
0.3 ClkOut_en=0 PA2-0=000, PA off 4 7.0 1.8 140 200 16MHz, 9pF load, XCO_Fast=1 VCPOUT = 1.2V, CP_CUR = 3 300 100 10 -7 1.5 3.0 18 9.6 5.6 60 20 300 20 200 20 50 200 5.6 40
MHz ms ms s s s A dBm dBm dB dB mA mA mA dB dB kHz kbps kbps kbps
ASK=7 (OOK) ASK=6 Bitrate = 200kbps VCO modulation Divider modulation ASK
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Electrical Characteristics (cont.)
Parameter Condition FSK 38.4kbps, = 2, bandwidth for 99.5% of total power, RBW=10kHz FSK 125kbps, = 2, bandwidth for 99.5% of total power, RBW=30kHz FSK 200kbps, = 2, bandwidth for 99.5% of total power, RBW=100kHz ASK (OOK) 38.4kbps, bandwidth for 99.5% of total power, RBW=10kHz ASK 20dB modulation depth, 38.4kbps, bandwidth for 99% of total power, RBW=10kHz 2 Harmonic 3 Harmonic Spurious Emission<1GHz Spurious Emission>1GHz LO Leakage
Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. On the pins RFVDD (3), PTATBIAS (6), DVDD (9), CPOUT (20), VARIN (21) and AVDD (23), the maximum input voltage should not exceed 2.75V. 4. Devices are ESD sensitive. Handling precautions recommended. Pin 4, RFOUT, has less ESD protection (Human body model (HBM) of 200V and Charged Device Model (CDM) of 500V). 5. Guaranteed by design.
rd nd
Min
Typ 130 425 750 200 120
Max
Units kHz kHz kHz kHz kHz
Occupied bandwidth
-36 -54 Measured with matching network -54 -41 -80
dBm dBm dBm dBm dBm
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MICRF405 desktop register controlling the state of the 405, the PA and clock-out for the microcontroller. The next block of 10bytes sets the output radio frequency through the dividers A, N and M. The bytes with address 11 to 21 set the frequency band, modulation type, bit rate, loop filter type and bandwidth, XCO tuning etc. This block is not frequently used as these settings are usually static application dependent. Address 22 and 23 are mostly test bits, and are seldom altered from default settings in applications. The interrupt register, which is located at address 24, is read only (writing to it will not do any harm or have any effect). The last 5 bytes are used when transferring user data to transmit through the SPI. The first four set the SyncID field in the packet, and the last is the one byte data buffer.
Data D7 Mode1=0 N0_7=0 M0_7=0 N1_7=0 M1_7=0 LowBatt_en=1 LowBatt_level=0 Bit_IO_en=1 Mod_I4=0 VCO_Fr_Chk=0 0 ASK_PN_en=0 ASKn1=1 INT_LF_EN=1 LF_High_PM=1 ClkOut_1=0 D6 Mode0=1 N0_6=1 M0_6=0 N1_6=1 M1_6=0 Freq_Band1=0 LDO_by=0 Manchester_en=0 Mod_I3=1 VCO_Fr_Auto=0 Prescaler_Sel=0 ASK_EN=0 ASKn0=0 CP_CUR1=0 LF_CAP1=1 ClkOut_0=0 VCO_IB2=0 PA_IB2 =0 VCO_freq_O1 SyncID3_6=1 SyncID2_6=1 SyncID1_6=1 SyncID0_6=1 DATA_6 D5 PA2=1 A0_5=0 N0_5=1 M0_5=1 A1_5=0 N1_5=1 M1_5=1 Freq_Band0=1 LDO_en1=1 Sel_CRC1=1 Mod_I2=0 FSKn2=1 FSKClk_K5=1 ASKshape2=1 ASKClk_K5=1 CP_CUR0=1 LF_CAP0=1 XCO_Fast=1 VCO_IB1=0 PA_IB1=0 VCO_freq_O0 SyncID3_5=1 SyncID2_5=1 SyncID1_5=1 SyncID0_5=1 DATA_5 SyncID3_4=0 SyncID2_4=0 SyncID1_4=0 SyncID0_4=0 DATA_4 SyncID3_3=0 SyncID2_3=0 SyncID1_3=0 SyncID0_3=0 DATA_3 D4 PA1=1 A0_4=0 N0_4=1 M0_4=0 A1_4=1 N1_4=0 M1_4=0 VCO_freq2=0 LDO_en0=1 Sel_CRC0=1 Mod_I1=0 FSKn1=0 FSKClk_K4=1 ASKshape1=1 ASKClk_K4=1 LF_RES1_4=0 LF_RES3_4=0 XCOtune4=1 VCO_IB0=0 PA_IB0=1 D3 PA0=1 A0_3=1 N0_11=0 N0_3=0 M0_11=0 M0_3=0 A1_3=1 N1_11=0 N1_3=1 M1_11=0 M1_3=0 VCO_freq1=1 MOD_LDc_en=0 SyncID_Len1=0 Mod_I0=1 FSKn0=0 FSKClk_K3=0 ASKshape0=1 ASKClk_K3=0 LF_RES1_3=1 LF_RES3_3=0 XCOtune3=0 VCO_by=0 PAB_IB3=1 D2 ClkOut_en=1 A0_2=1 N0_10=0 N0_2=0 M0_10=0 M0_2=0 A1_2=1 N1_10=0 N1_2=1 M1_10=0 M1_2=0 VCO_freq0=1 PA_FEc_en=0 SyncID_Len0=1 Mod_A2=0 Mod_F2=1 FSKClk_K2=1 ASK2=1 ASKClk_K2=1 LF_RES1_2=0 LF_RES3_2=1 XCOtune2=0 OUTS2=0 PAB_IB2=0 VC_HI SyncID3_2=1 SyncID2_2=1 SyncID1_2=1 SyncID0_2=1 DATA_2 D1 Sync_en=1 A0_1=1 N0_9=0 N0_1=1 M0_9=0 M0_1=0 A1_1=1 N1_9=0 N1_1=1 M1_9=0 M1_1=0 Modulation1=1 PA_LDc_en=0 Pream_Len1=1 Mod_A1=1 Mod_F1=0 FSKClk_K1=0 ASK1=1 ASKClk_K1=0 LF_RES1_1=0 LF_RES3_1=0 XCOtune1=0 OUTS1=0 PAB_IB1=0 VC_LO SyncID3_1=0 SyncID2_1=0 SyncID1_1=0 SyncID0_1=0 DATA_1 D0 Load_en=1 A0_0=0 N0_8=0 N0_0=1 M0_8=0 M0_0=1 A1_0=1 N1_8=0 N1_0=1 M1_8=0 M1_0=0 Modulation0=0 LD_en=1 Pream_Len0=0 Mod_A0=1 Mod_F0=0 FSKClk_K0=0 ASK0=1 ASKClk_K0=0 LF_RES1_0=1 LF_RES3_0=1 XCOtune0=0 OUTS0=0 PAB_IB0=1 LOW_BATT SyncID3_0=1 SyncID2_0=1 SyncID1_0=1 SyncID0_0=1 DATA_0
Data and Configuration Interface
The user interface of the MICRF405 is a serial peripheral interface (SPI) consisting of Serial interface enable (SEN), Serial data input/output (SIO) and Serial clock (SCK). This user interface is used for MICRF405 configuration setup and can also be used for sending the user data. A second option is to transmit data bitwise using the DATAIN pin. The RDY/DATACLK pin is used to synchronize the data transfers. The control word consists of 30 addressable bytes and defines the way of operations as well as transmitting data. Table 1 shows all 30 bytes. The values specified are the default setup, which are preset after power up. The first register is the
Adr A6..A0 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101
0010110 INT_LF_TEST=0 0010111 0011000 0011001 0011010 0011011 0011100 0011101 PA_IB3=1 VCO_freq_O2 SyncID3_7=1 SyncID2_7=1 SyncID1_7=1 SyncID0_7=1 DATA_7
Table 1. Controlword MICRF405 (values preset at power-up).
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Programming Interface Timing Figure 1 and Table 2 shows the timing specification for the 3-wire serial programming interface.
Figure 1. Programming Interface Timing.
Values Symbol Tper Thigh Tlow Tfall Trise Tsenf Tsenr Twrite Tread Trdy
Thigh
Parameter Min. period of SCK Min. high time of SCK Min. low time of SCK Max. time of falling edge of SCK Max. time of rising edge of SCK Min. time of falling edge of SEN to falling edge of SCK Min. delay from rising edge of SEN to rising edge of SCK Min. delay from valid SIO to falling edge of SCK during a write operation Min. delay from rising edge of SCK to valid SIO during a read operation (assuming load capacitance of SIO is 25pF) Min. delay from falling edge of SCK (last bit of byte into data buffer) to falling edge of RDY
Min. duration of a SEN high pulse (Fphd is the phase detector frequency) Time from power up to first falling edge of SEN
Min. 50 20 20
Typ.
Max.
Units ns ns ns
1 1 0 5 0 75 20
1/Fphd
s s ns ns ns ns ns
3.5
ms
Table 2. Timing Specification for the 3-wire Programming Interface.
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Writing to the Control Registers in MICRF405 Writing: A number of octets are entered into MICRF405 followed by a load-signal to activate the new setting. Making these events is referred to as a "write sequence." It is possible to update all, 1, or n control registers in a write sequence. The address to write to (or the first address to write to) can be any valid address (0-29). The SIO line is always an input to the MICRF405 (output from user) when writing.
Field Address: R/W bit: Values: Comments
What to write: * The address of the control register to write to (or if more than 1 control register should be written to, the address of the 1st control register to write to). * A bit to enable reading or writing of the control registers. This bit is called the R/W bit. * The values to write into the control register(s).
A 7-bit field, ranging from 0 to 29. MSB is written first. A 1-bit field, = "0" for writing A number of octets (1-30 octets). MSB in every octet is written first. The first octet is written to the control register with the specified address (="Address"). The next octet (if there is one) is written to the control register with address = "Address + 1" and so on. Table 3. Writing to the Control Registers.
How to write: Bring SEN low to start a write sequence. The active state of the SEN line is "low". Use the SCK/SIO serial interface to clock in "Address" and "R/W" bit and "Values" into the MICRF405. MICRF405 will sample the SIO line at negative edges of SCK. Make sure to change the state of the SIO line before the negative edge, for instance on positive edge. Refer to Figure 2. Bring SEN inactive to make an internal load-signal and complete the write-sequence. Note: there is an exception to this point. If the programming bit called "load_en" (D0 in ControlRegister0) is "0", then no load pulse is generated.
Field Address: R/W bit: Values: Comments 7 bit = A6, A5, ...A0 (A6 = MSB. A0 = LSB) "0" for writing 8 bits = D7, D6, ...D0 (D7 = MSB, D0 = LSB)
The two different ways to "program the chip" are: * Write to a number of control registers (0-29) when the registers have incremental addresses (write to 1, all or n registers) * Write to a number of control registers when the registers have non-incremental addresses. Writing to a Single Register Writing to a control register with address "A6, A5, ...A0" is described here. During operation, writing to 1 register is sufficient to change the way the transmitter works. Typical example: Change from transmit mode to power-down.
Table 4. When writing to a Single Register, totally 2 octets are clocked into the MICRF405.
How to write: * Bring SEN low * Use SCK and SIO to clock in the 2 octets * Bring SEN high
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Internal load pulse generated here
MICRF405
Register address SEN
Data to write into register
SIO
A6 A5 A4 A3 A2 A1 A0 R/W D7 D6D5 D4 D3 D2 D1 D0
SCK
Figure 2. Writing to One Address.
In Figure 2, SIO is changed at positive edges of SCK. The MICRF405 samples the SIO line at negative edges. The value of the R/W bits is always "0" for writing. Writing to All Registers Writing to all register can be done at any time. To get the simplest firmware, always write to all registers. The price to pay for the simplicity is increased write-time, which leads to increased time to change the way the MICRF405 works. If data is transferred through DATAIN pin write address 0-23 (address 24-29 is don't care). If data is transferred through SPI write address 0-28 (Address 29 is only written to during data transfer, not during configuration). What to write Field Address: R/W bit: Values: Comments `0000000' (address of the first register to write to, which is 0) "0" for writing 1 Octet: wanted values for ControlRegister0. 2 so on for all of the octets.
st nd
Octet: wanted values for ControlRegister1 and
Table 5. When writing to All Registers, totally 25/30 (5 are optional) octets are clocked into the MICRF405.
How to write: * Bring SEN low * Use SCK and SIO to clock in the 25/30 octets * Bring SEN high Refer to Figure 3. Writing to n Registers Having Incremental Addresses.
Writing to n Registers Having Incremental Addresses In addition to entering all bytes, it is also possible to enter a set of n bytes, starting from address i = "A6, A5, ... A0". Typical example: Clock in a new set of frequency dividers (i.e. change the RF frequency). Registers to be written are located in i, i+1, i+2.
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What to write
Field Address: R/W bit: Values: Comments 7 bit = A6, A5, ...A0 (A6 = MSB. A0 = LSB) (address of first byte to write to) "0" for writing n* 8 bits = D7, D6, ...D0 (D7 = MSB, D0 = LSB) (written to control reg. with address "i") D7, D6, ...D0 (D7 = MSB, D0 = LSB) (written to control reg. with address "i+1") D7, D6, ...D0 (D7 = MSB, D0 = LSB) (written to control reg. with address "I+n-1") Table 6. When writing to Registers having Incremental Addresses, totally 1+n octets are clocked into the MICRF405.
How to write:
* Bring SEN low * Use SCK and SIO to clock in the 1 + n octets * Bring SEN high
Internal load pulse generated here
Register i address SEN
Data to write into register i
Data to write into register i +1
Data to write into register i+n-1
SIO
A6 A5
A0 R/W D7 D6
D0 D7 D6
D0
D7 D6
D0
SCK
Figure 3. Writing to n Registers Having Incremental Addresses.
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Writing to n Registers having Non-Incremental Addresses Registers with non-incremental addresses can be written to in one write-sequence as well. Example of non-incremental addresses: "0,1,3". However, this requires more overhead, and the user should consider the possibility to make a "continuous" update, for example, by writing to "0,1,2,3" (writing the present value of "2" into "2"). The simplest firmware is achieved by always writing to all registers. Refer to previous sections. This write-sequence is divided into several subparts: * Disable the generation of load-signals by clearing bit "load_en" (D0 in ControlRegister0) * Repeat for each group of register having incremental addresses: - Bring SEN active - Enter first address for this group, R/W bit and values - Bring SEN inactive * Finally, enable and make a load-signal by setting "load_en" Refer to the previous sections for how to write to 1 or n (with incremental addresses) registers in the MICRF405. Reading from the Control Registers in MICRF405 The "read-sequence" is: 1. Enter address and R/W bit 2. Change direction of SIO line 3. Read out a number of octets and change SIO direction back again. It is possible to read all, 1 or n registers. The address to read from (or the first address to read from) can be any valid address (0-29). Reading is not destructive, i.e., values are not changed. The SIO line is output from the MICRF405 (input to user) for a part of the read-sequence. Refer to procedure description below. A read-sequence is described for reading n registers, where n is number 1-30.
Register address SEN
Data read from register
Internal load pulse generated here
SIO
A6 A5 A4 A3 A2 A1 A0 R/W D7 D6D5 D4 D3 D2 D1 D0
SCK
SIO INPUT SIO OUTPUT SAMPLE TIME
Figure 4. Reading from a Control Register.
In Figure 4 above, 1 register is read. The address is A6, A5, ... A0. A6 = MSB. The data read out is D7, D6, ...D0. The value of the R/W bit is always "1" for reading. * Bring SEN low * Enter address to read from (or the first address to read from) (7 bits) and * The R/W bit = 1 to enable reading * Make the SIO line an input to the user (set pin in tristate) * Read n octets. The first rising edge of SLK will set the SIO as an output from the MICRF405. The 405 will change the SIO line at positive edges of SCK. The user should read the SIO line at the negative edges. * Make the SIO line an output from the user again. Reading from the Interrupt Register If any of the interrupts, Vc_HI, Vc_LO or Low_Batt, is set the SRV pin will go high. Read the interrupt register, address 24, to see which interrupts are flagged. It is possible to read this register at all times, for instance, to read the tuned VCO_FREQ setting which is also stored at the same address. When rising SEN after haveing read the register, the internal load pulse will then clear all interrupt flags. To keep the flags when reading it, it is therefore necessary to set LOAD_en=0 before hand.
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Data Interface and Data Transfer
Adr A6..A0 0000000 0001100 0001101 0011001 0011010 0011011 0011100 0011101 D7 Mode1=0 LowBatt_level=0 Bit_IO_en=1 SyncID3_7=1 SyncID2_7=1 SyncID1_7=1 SyncID0_7=1 DATA_7 D6 Mode0=1 LDO_by=0 Manchester_en=0 SyncID3_6=1 SyncID2_6=1 SyncID1_6=1 SyncID0_6=1 DATA_6 D5 PA2=1 LDO_en1=1 Sel_CRC1=1 SyncID3_5=1 SyncID2_5=1 SyncID1_5=1 SyncID0_5=1 DATA_5 D4 PA1=1 LDO_en0=1 Sel_CRC0=1 SyncID3_4=0 SyncID2_4=0 SyncID1_4=0 SyncID0_4=0 DATA_4 Data D3 PA0=1 MOD_LDc_en=0 SyncID_Len1=0 SyncID3_3=0 SyncID2_3=0 SyncID1_3=0 SyncID0_3=0 DATA_3 D2 ClkOut_en=1 PA_FEc_en=0 SyncID_Len0=1 SyncID3_2=1 SyncID2_2=1 SyncID1_2=1 SyncID0_2=1 DATA_2 D1 Sync_en=1 PA_LDc_en=0 Pream_Len1=1 SyncID3_1=0 SyncID2_1=0 SyncID1_1=0 SyncID0_1=0 DATA_1 D0 Load_en=1 LD_en=1 Pream_Len0=0 SyncID3_0=1 SyncID2_0=1 SyncID1_0=1 SyncID0_0=1 DATA_0
There are two main data interfaces; bit-wise and byte oriented. The bit-wise interface use the DATAIN (always input to the 405) and DATACLK pin (always output from the 405). This interface is enabled with the Bit_IO_en="1". If Sync_en=1 bit-wise synchronous mode is selected and data clock is provided on the RDY/DATACLK pin. In this mode, the MICRF405 will sample the bit on the DATAIN pin on the positive edge of the DATACLK. It is therefore important that the MCU toggle the DATAIN pin on negative edge of the DATACLK, See Figure 5. No packet engine, CRC or Manchester encoding is available in bit-wise data interface. To select asynchronous mode set Sync_en="0". If VCO modulation is selected, the DATAIN pin in tri-state (MCU pin=input) until first bit is about to be transmitted (see VCO modulation).
DATAIN
DATACLK
Figure 5. Synchronous Data Interface.
If Bit_IO_en=0, the byte wise interface is selected and data is transferred byte wise through the one byte buffer (register address 29). The register is accessed the same way as the other register, as explained in the previous sections. The only difference is that it is instantly valid and do not need any load pulse. This also applies to the SyncID registers, address 25-28. When writing to address 29, the address counter will not increment which means several bytes can be written into the buffer without raising SEN and setting up a new write session. The RDY/DATACLK pin will provide byte synchronization. The data byte buffer is ready for refill on falling edges on RDY. In this mode of data transfer, Sync_en must be set.
The data in the buffer is fed into a packet engine with an optional CRC calculation and Manchester encoding. The virtual wire packet structure is shown in Table 7. The preamble, SyncID field and CRC field are automatically generated by the packet engine. The user needs only to enter frame length and payload for each packet. The preamble bytes are equal to 10101010, and the number of preamble bytes are given by 1+Pream_Len[1:0] (D1:D0 ControlRegister13). Next field is the SyncID which is 1-4 bytes long set by the SyncID_Len[1:0] bits. The content of the SyncID bytes are fully programmable and specified in the SyncID0-3 bytes. The SyncID0 byte, address 28, is sent first, and the SyncID3 byte, address 25, is sent last. Refer to Table 8. The frame length byte follows the SyncID field. It specifies length of the payload and CRC. Finally, the CRC field ends the packet. The SelCRC_0 bit specifies the length of the CRC field. If it is set, a 2 byte ITU-T CRC (start condition 00h) is calculated of the payload and sent. If SelCRC_0=0, an 8 bit CCITT CRC is calculated of the payload and sent. Either two cases assuming SelCRC_1=1. If SelCRC_1=0, no CRC is calculated on chip, and the user must calculate this on the microcontroller and include it in the payload. A Manchester encoder is available on chip. It is activated if the Manchester_en bit is set. It encodes the complete packet. The codes are "10" for "0" and "01" for "1". The preamble byte is automatically set 0 in this mode, as this will produce the desired 10101010-pattern when Manchester encoded. Note that on-the-air data rate will be twice the bit rate set by the FSKClk_K/FSKn or ASKClk_K/ASKn, which specifies the actual throughput. Because of this, FSKn needs to be greater than zero if VCO modulation is selected, Modulation[1:0]<2.
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MICRF405
Preamble 1-4 bytes
SyncID 1-4 bytes
Frame length 1 byte
Payload 2/2/1-253/254/255 bytes
CRC 2/1/0 bytes
Table 7. Virtual Wire Packet Structure Overview.
SyncID_Len
0 0 1 1
SynchID_Len
0 1 0 1
Start of transmitted packet. Leftmost byte transmitted first
Preamble Preamble Preamble Preamble SyncIDO SyncIDO SyncIDO SyncIDO Frame length SyncID1 SyncID1 SyncID1 Frame length SyncID2 SyncID2 Frame length SyncID3 Frame length
Table 8. Virtual Wire Packet Structure, SyncID field.
Packet Engine Overview: * Preamble generated by packet engine: 1-4 bytes equal 10101010. Length set by Pream_Len[1:0] * SyncID field added by packet engine: 1-4 bytes of user defined content. Length set by SyncID_Len[1:0]. Content set in registers SyncID0, SyncID1, SyncID2 and SyncID3, address 28-25. * The frame length is entered by user for each packet. Specify the length of the payload and CRC fields in bytes, ranging from 2 to (255 / # CRC bytes). # CRC bytes can be 0 to 2. * For each payload byte, wait for falling edge of RDY before writing the byte into the DATA register. * The optional CRC field ends the packet. Its length is programmable 0, 1 or 2 bytes by the Sel_CRC[1:0].
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MICRF405
How to transmit a Packet with the Packet Engine:
Send data
PROG
CALL PROG [TX] INIT WRITE SEQUENCE [SET SEN="0"]
INIT WRITE SEQUENCE [SET SEN="0"]
MICRF405 starts the XCO. When XCO is stable the MICRF405 powers up the LDOs and starts the PLL.
Control word, e.g: TX mode:
Mode1-0=3 [TX] PA_LDc="1"[Turns on PA stage when PLL is in lock] MOD_LDc_en="1" [Modulation starts once frame length is written into data byte and PA is turned on and LD is high.] PA_FEc_en="1" [The PA is turned off immediately after last bit in packet is sent.]
INIT TX BUFFER [WRITE ADDR 29, R/W ="0"]
WRITE CONTROL WORD [ADDRESS + R/W + CONTROL WORD]
Power down mode:
Mode1-0=0 LOAD CONTROL WORD [SET SEN="1"]
WRITE FRAME LENGTH
RETURN PLL IN LOCK? [LD="1"] YES NO
TURN on PA
MICRF405 waits for the PLL to lock; LD="1", Turns on PA and waits for the PLL to lock with PA on; "LD=1", then start to send Preamble, SyncID and Frame length. NO
PLL IN LOCK? [LD="1"]
YES MICRF405 INTERNAL PROCESS
i=0
RDY = falling edge? YES
NO Wait for [2 + number of CRC bytes] falling edge of RDY. Then wait 1 bit periode.
WRITE PAYLOAD BYTE i END TX msg sequence [SEN="1"]
i=1+1
CALL PROG [Power down] i=n? NO
YES
END
Figure 6. Flowchart of Transmitting a Packet Using the Packet Engine.
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MICRF405 means that the SEN now can be pulled high at any time, closing the write session. If PA_LDc_en=1 and load_en=1, it is then necessary to leave SEN low until the end of packet. This is because raising SEN will generate a load pulse, and this, in turn, causes the PA_LDc function to turn off the PA for a short period of time. The RDY signal will be high when the last bit of the payload is being sent, but there is now no need to refill the buffer. Also, if CRC is enabled, then RDY will be high during the last bit of each of the CRC bytes being sent. Because of an internal sampling the actual RF output lags 1 bit period, which means the modulation will stop one bit period after the last RDY pulse. 6. The frame is now completely transmitted. If PA_FEc_en=1, the PA will be automatically turned off immediately after last bit in packet is transmitted. The PLL will, however, remain running. (This state is equal to MODE[1:0]=3 (TX), PA_LDc_en=0 and PA[2:0]=0.) If PA_FEc_en=0 the PA will remain on until it is turned off by the MODE or PA bits. In step 6, the buffer is ready for a new packet. Any 8bits entered into the buffer in this sections is though of as a new frame length, refer back to Section 3. This, assuming the MICRF405 remains in TX (MODE[1:0]=3). In this case, and when PA_FEc_en=1, the PA will be turned th on once the 8 bit is clocked in. It is recommended to use the MOD_LDc function in this case as it will delay the modulation until the PLL has stabilized after the PA is turned on. If not the start of the modulation will be distorted and may interfere the settling of the PLL due to PA turn on (please see chapter Lock Detect).
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MICRF405
Figure 7. Sequence of a Typical Packet Transfer.
Programming Summary * Use SEN, SCK, and SIO to get access to the control registers in MICRF405. * SCK is user-controlled. * Write to the MICRF405 on positive edges (MICRF405 reads on negative edges). * Read from the MICRF405 on negative edges (MICRF405 writes on positive edges) * Address field is 7 bits long. Enter MSB first. * R/W bit is "1" for read and "0" for write. * Address and R/W bit together make 1 octet * Enter/read MSB in every octet first. * Always write 8 bits to/read 8 bits from a control register. This is the case for registers with less than 8 used bits as well. * Writing: Bring SEN low, write address and R/W bit followed by the new values to fill into the addressed control register(s) and bring SEN high for loading, i.e. activation of the new control register values ("Load_en" = 1).
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MICRF405
Main Modes of Operation
Adr A6..A0 0000000 D7 Mode1=0 D6 Mode0=1 D5 PA2=1 D4 PA1=1 D3 PA0=1 Data D2 ClkOut_en=1 D1 Sync_en=1 D0 Load_en=1
There are three main modes of operation and these are controlled by Mode1-0, see Table 9. In "Power down" mode all blocks are shut down, though the contents of the registers are preserved. In "Standby" the crystal oscillator is running and an optional programmable clock is present on the CLKOUT pin (Default enabled). This clock can be used as a micro-controller reference frequency. In "TX" mode all blocks are active if not disabled by the user.
Mode1 Mode0 0 0 1 1 0 1 0 1
State Power down Standby Transmit mode
Comments Keeps Register configuration Crystal Oscillator running Transmit mode
Table 9. MICRF405 Main Modes.
Power Amplifier
Adr A6..A0 0000000 0010111 D7 Mode1=0 PA_IB3=1 D6 Mode0=1 PA_IB2 =0 D5 PA2=1 PA_IB1=0 D4 PA1=1 PA_IB0=1 Data D3 PA0=1 PAB_IB3=1 D2 ClkOut_en=1 PAB_IB2=0 D1 Sync_en=1 PAB_IB1=0 D0 Load_en=1 PAB_IB0=1
The maximum output power is approximately 10dBm. For maximum output power the load seen by the PA must be resistive and around 150 at 900MHz and 250 at 434MHz and 315Hz. The output power can be programmed with bits PA[2:0] to eight different levels if bit PA_LDc_en=1 or seven levels if PA_LDc_en=0, with approximately 3dB between each step. If PA_LDc_en=0, the PA is turned of by setting PA[2:0] to 0. For all other PA[2:0] combinations, the PA is on and has a maximum power when PA[2:0]=7. If PA_LDc_en=1 the PA is controlled by the lock detector. A simple LC network can be used to provide the
Frequency band (MHz) 315 434 868 915
needed impedance and also to reduce the power of the harmonics to acceptable levels. Such matching networks for different frequencies are shown on the Typical Application Circuit. The bias setting of the PA and the PA buffer is controlled by bits PA_IB PA[2:0] and PAB_IB PA[2:0]. The recommended bit setting, shown in Table 10, is for the different frequency bands. Typical values of output power and current consumption for the different power levels for different frequencies are shown in Table 11. The settings used are: Modulation[2:0]=2, ClkOut_en=0, external loop filter.
PAB_IB[2:0] 8 8 9 9
PA_IB[2:0] 8 9 9 10
Table 10. Recommended Settings of PA_IB and PAB_IB vs. Frequency Band.
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MICRF405
Power level (PAx) 7 6 5 4 3 2 1 0 PA off
915MHz Pout (dBm) 10.0 5.8 3.1 0.5 -1.9 -4.2 -6.7 -9.2 IVDD (mA) 17.5 13.2 11.5 10.5 9.9 9.5 9.1 8.9 5.4
434MHz Pout (dBm) 10.3 7.0 4.3 1.7 -1.1 -3.8 -6.8 -9.8 IVDD (mA) 16.8 13.0 11.6 10.6 10.0 9.5 9.2 9.0 6.1
315MHz Pout (dBm) 10.5 8.6 5.7 2.8 -0.1 -3.2 -6.5 -9.7 IVDD (mA) 16.4 13.3 11.5 10.2 9.3 8.6 8.2 7.9 5.4
Table 11. Output Power and Current Consumption vs. Power Level Setting (PA2..PA1) for 315, 434 and 915MHz.
Frequency Synthesizer
Adr A6..A0 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0010000 D7 N0_7=0 M0_7=0 N1_7=0 M1_7=0 `0' D6 N0_6=1 M0_6=0 N1_6=1 M1_6=0 Prescaler_Sel=0 D5 A0_5=0 N0_5=1 M0_5=1 A1_5=0 N1_5=1 M1_5=1 FSKClk_K5=1 D4 A0_4=0 N0_4=1 M0_4=0 A1_4=1 N1_4=0 M1_4=0 FSKClk_K4=1 Data D3 A0_3=1 N0_11=0 N0_3=0 M0_11=0 M0_3=0 A1_3=1 N1_11=0 N1_3=1 M1_11=0 M1_3=0 FSKClk_K3=0 D2 A0_2=1 N0_10=0 N0_2=0 M0_10=0 M0_2=0 A1_2=1 N1_10=0 N1_2=1 M1_10=0 M1_2=0 FSKClk_K2=1 D1 A0_1=1 N0_9=0 N0_1=1 M0_9=0 M0_1=0 A1_1=1 N1_9=0 N1_1=1 M1_9=0 M1_1=0 FSKClk_K1=0 D0 A0_0=0 N0_8=0 N0_0=1 M0_8=0 M0_0=1 A1_0=1 N1_8=0 N1_0=1 M1_8=0 M1_0=0 FSKClk_K0=0
Figure 8. PLL Block Diagram.
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MICRF405
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MICRF405
Crystal Oscillator (XCO)
Adr A6..A0 D7 D6 D5 D4 XCOtune4=1 D3 XCOtune3=0 Data D2 XCOtune2=0 D1 XCOtune1=0 D0 XCOtune0=0
0010101 ClkOut_1=0 ClkOut_0=0 XCO_Fast=1
The crystal oscillator is a very critical block. As the crystal oscillator is a reference for the RF output frequency, very good phase and frequency stability is required. When selecting crystal it should be paid special attention to the total frequency tolerance and load capacitance as these will directly influence on the carrier frequency.
capacitors must be added off-chip (C1 and C2 in Figure 9). If XCOtune[4:0]=0, the loading capacitors can be calculated by the following formula;
CL = 1 + Cparasitic 1 1 + C1 C2
XTB, pin 7
XTA, pin 8
C1
C2
Figure 9. Crystal Oscillator Circuit.
The crystal should be connected between pins XTA and XTB (pin 7 and 8). MICRF405 has an internal crystal capacitor bank used for crystal tolerance tuning during production. These internal capacitors can be enabled using the XCOtune[4:0] bits. If XCOtune[4:0]=0 then no internal capacitors are connected to the crystal pins, while 18pF are connected to each pin if XCOtune[4:0]=31. The unit capacitance is about 0.6pF. The internal XCOtune feature is optimized for a crystal with a load capacitance of 9pF and will give the expected oscillation frequency when no external capacitors are connected and XCOtune[4:0]=16. If a crystal requires higher load capacitance, additional
The parasitic capacitance is the pin input capacitance and PCB stray capacitance. Typically the total parasitic capacitance is around 6pF. For instance, for a 9pF load crystal the recommended values of the external load capacitors are 5.6pF. The start-up time of a crystal oscillator is typically around a millisecond. Therefore, to save current consumption, the XCO is turned on before any other circuit block. During start-up the XCO amplitude will eventually reach a sufficient level to trigger the Mcounter. After counting 2 M-counter output pulses the rest of the circuit will be turned on. The current consumption during the prestart period is typically 205A. If the XCO_Fast bit is set, then XCO will start up faster, typically in about 300s. This comes at the expense of a higher current consumption of typically 2mA during the period from start up until the first output pulse of the M-divider. If an external reference shall be used instead of a crystal, the signal shall be applied to pin 7, XTB. Due to internal biasing, AC coupling is recommended for use between the external reference and the XTB-pin.
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MICRF405
VCO
Adr A6..A0 0001011 0010110 0011000 D7 LowBatt_en=1 INT_LF_TEST=0 VCO_freq_O2 D6 Freq_Band1=0 VCO_IB2=0 VCO_freq_O1 D5 Freq_Band0=1 VCO_IB1=0 VCO_freq_O0 D4 VCO_freq2=0 VCO_IB0=0 Data D3 VCO_freq1=1 VCO_by=0 D2 VCO_freq0=1 OUTS2=0 VC_HI D1 Modulation1=1 OUTS1=0 VC_LO D0 Modulation0=0 OUTS0=0 LOW_BATT
The VCO has no external components. It oscillates at 1.8 GHz and is divided by 2, 4 and 6 in the 900 MHz, 450 MHz or 315MHz band respectively. This divide ratio is controlled by the Freq_Band[1:0] bits, as shown in Table 12.
FreqBand1 FreqBand0 0 0 1 0 1 X Comments RF frequency 290-325 MHz RF frequency 430-490 MHz RF frequency 860-980 MHz
Table 12. Frequency Band.
The VCO_IB setting is automatically set when VCO_IB[2:0]=0. If VCO_IB[2:0] are programmed <> 0, it will overrule the automatic setting. Default and recommended for automatic settings, is VCO_IB[2:0]=0 for all frequencies. The bias bits will optimize the phase noise, and the frequency bits will control a capacitor bank in the VCO. The tuning range, the RF frequency versus varactor voltage, is dependent upon the VCO frequency setting, and is shown in Figure 10. When the tuning voltage is in the range from 1.2 to 1.6V, then the VCO gain is at its maximum, approximately 60-80 MHz/V. It is recommended that the varactor voltage is kept within this range. Table 15 shows the recommended settings of VCO_freq and FreqBand for various frequencies. To ensure correct settings over variations, a circuit monitoring the varactor voltage on start up is added. When the PLL has locked, or after a timeout has occurred if it doesn't lock, this circuit will control the varactor voltage. This will be performed if either the VCO_Fr_Chk or VCO_Fr_Auto bit is set. VCO_Fr_Chk set will set the interrupts VC_HI, in case of a too high VCO_freq setting creating a too high varactor voltage, and VC_LO, in case of a too
low VCO_freq setting creating a too low varactor voltage. If the VCO_Fr_Auto bit is set, then the transmitter will, if the varactor voltage is out of range, change the programmed VCO_freq setting until the voltage is within the range. A new setting will remain active as long as power is on, VCO_Fr_Auto is set and the programmed VCO_freq[2:0] bits are not altered. The tuned VCO_freq setting of the automatic tune circuit can be read out in the interrupt register, VCO_Freq_O[2:0]. If both VCO_Fr_Chk and VCO_Fr_Auto are set, each step is done by the automatic tuning circuit that will be flagged with a VC_LO or VC_HI interrupt. The limits of varactor voltage used by this control circuit are between 350mV and 350mV below AVDD. The check is performed when entering TX mode. If PA_LDc_en=1, the control will also be executed for each programming creating an internal load pulse (load_en=1) while staying in TX mode. This means that when changing frequency, the MICRF405 will check that the VCO_Freq[2:0] settings are correct for the new frequency. Refer to Table 13 and Table 14 for further details. The MICRF405 must be programmed with the recommended settings for FreqBand and VCOfreq, as given in Table 15, even if the VCO_Fr_Chk and VCO_Fr_Auto are enabled. This is needed to give the VCO the correct starting values. The VCO can be bypassed by applying a differential local oscillator (LO) signal to the device on pin CPOUT and VARIN. A resistor of 18k to ground and a series capacitor of 47pF are needed on both pins for proper biasing. The bit VCO_by must be set to 1.
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MICRF405
VCO_Fr_Chk 0 1
Comments VCO control voltage is not controlled VCO control voltage is measured; if it is below 0.35V the VC_LO interrupt flag is set, if it is higher than AVDD-0.35V the VC_HI flag is set Table 13. VCO Control Voltage Out of Range Detection.
VCO_Fr_Auto 0
Comments No calibration is done. If VCO control voltage is below 0.35V or above AVDD-0.35V, the VCO frequency settings are altered until the control voltage is within the window. No VC_LO or VC_HI interrupt flag is set. The new settings can be read out; bits VCO_Freq_O[2:0] in interrupt register. If PLL for some reason cannot obtain lock (i.e. if frequency is set wrongly), an interrupt will be given even if VCO_Fr_Chk = 0. Table 14. Automatic VCO Range Calibration.
1
VCO Tuning Range for Various VCO_Freq Settings
1050.0
1000.0 7 RF frequency [MHz] 6 950.0 5 4 3 900.0 2 1 0 850.0
800.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Varactor Voltage [V]
Figure 10. RF Frequency vs. Varactor Voltage and VCO Frequency Bit.
VCO_freq
FreqBand=0 315MHz
FreqBand=1 433MHz
FreqBand=2 or 3 868, 915MHz
1 2 3 4 5 6 7
287 290 293 300 307 313 320
290 293 300 307 313 320 326
430 435 440 450 460 470 480
435 440 450 460 470 480 490
860 870 880 900 920 940 960
870 880 900 920 940 960 980
Table 15. Freq Ranges vs. VCO_freq and FreqBand.
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Charge Pump and PLL Filter
Adr A6..A0 0010011 0010100 0010110 D7 INT_LF_EN=1 LF_High_PM=1 INT_LF_TEST=0 D6 CP_CUR1=0 LF_CAP1=1 VCO_IB2=0 D5 CP_CUR0=1 LF_CAP0=1 VCO_IB1=0 D4 LF_RES1_4=0 LF_RES3_4=0 VCO_IB0=0 Data D3 LF_RES1_3=1 LF_RES3_3=0 VCO_by=0 D2 LF_RES1_2=0 LF_RES3_2=1 OUTS2=0 D1 LF_RES1_1=0 LF_RES3_1=0 OUTS1=0 D0 LF_RES1_0=1 LF_RES3_0=1 OUTS0=0
There are two charge pumps, one for the external loop filter, and one for the internal filter. Both pumps have four different output current steps controlled by the CP_CUR[1:0] bits (refer to Table 16). The internal loop filter is a dual path type, which needs two charge pump currents. The different steps allow different bandwidths for the internal filter and give greater flexibility when choosing components for the external filter. An external PLL loop filter is recommended when using FSK modulation that is applied with dividers and closed loop modulation using the modulator. For Open Loop modulation a combination of external and internal loop filter is recommended. In all modes of ASK/OOK modulation, it is only possible to use internal PLL loop filter due to the high bandwidth requirements. Table 15 below shows three different loop filters, the three first are for closed loop modulation and the last one is for open loop modulation. The component values are calculated with RF frequency = 915MHz, VCO gain = 67MHz/V and charge pump current = 100uA. Other settings are also shown in Table 15. The varactor pin capacitance of 10-12pF does not influence on the component values for the two filters with lowest bandwidth. For the 12kHz bandwidth filter, a third order loop filter is calculated. The third pole is set by R2 andC3. Here C3 is chosen to be 12pF, the same as the varactor input pin capacitance. C3 can therefore be skipped.
A schematic for a third order loop filter is shown in Figure 11a. For a second order filter, C3 is not connected and R2 is 0 . When designing a third order loop filter, the internal capacitance on the VARIN pin of approximately 10-12pF must be taken into consideration. Figure 11b shows the loop filter configuration for the open loop VCO modulation case. The on-chip dual path filter is shown in Figure 11c. The dual path loop filter has capacitance configurable in four steps, by the LF_CAP[1:0] bits. The ratio between C1 and C2 in Figure 11 c) sets the phase margin of the filter. If LF_High_PM bit is not set the phase margin is 56, if it is set the phase margin is 69. The R1 and R3 resistor value is set separately in 32 steps by the LF_RES1[4:0] and LF_RES3[4:0] bits. The on-chip dual path filter can be used when the modulation type is set to Open-Loop VCO or ASK. Table 18 gives the recommended settings for the internal component values for various bitrates and phase detector frequencies. The settings are calculated to give optimal phase margin for the given phase-frequency-detector frequency and loop filter bandwidth. (More values of C and R can be found in Table 52 and Table 52 on page 40 and 41).
CP_CUR1 0 0 1 1
CP_CUR0 0 1 0 1
External Charge Pump Current 12.5A 25A 50A 100A Table 16. Charge Pump.
Internal Charge Pump Current 1.25/12.5A 3.125/31.25A 6.25/62.5A 12.5/125A
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MICRF405
Mod. Type VCO VCO Divider Divider Divider Divider Open loop
Freq [MHz] All All 315 433 868 915 All
Baud Rate [kbaud/ sec] > 30 > 100 < 20 < 20 < 15 < 20 < 200
Coding Manchester Manchester DC-free DC-free DC-free DC-free DC-free
PLL BW [kHz] 0.8 3.0 17 18 20 21 26
Phase margin [] 56 56 60 60 51 60 56
Phase detector Freq. [kHz] 100 100 500 500 700 500 500
C1 [nF] 10 0.68 0.068 0.068 0.082 0.047 0.047
C2 [nF] 100 68 6.8 6.8 4.7 4.7 0.47
R1 [k] 6.2 27 30 30 27 36 43
R2 [k] 75 75 75 91 NC
C3 [pF] 12 12 18 5.6 33000
Table 17. External Loop Filter Values.
CPO pin 20 UT,
R2
VARIN, pin 21
CPO pin 20 UT,
VARIN, pin 21
C1
C2
C3
C1
C2 47nF C3
R1
R1
a)
b)
C1
CP, internal CP, internal
+
R3
VARIN, internal
C3 R1 C2
Vref c)
Figure 11. Loop filter for: a) Closed Loop Modulation, b) Open Loop Modulation and c) Internal Dual Path Filter.
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MICRF405
Modulation type Open loop VCO Open loop VCO ASK 4.8kbps ASK 9.6kbps ASK >9.6kbps
Fphd [kHz] 500 1000 1000 2000 2000
BW [kHz] 22.5 45 32 64 220
CP [uA] 3.125/31.25 6.25/62.5 3.125/31.25 6.25/62.5 12.5/125
CP_CUR 1 2 1 2 3
C1 [pF] 32.4 32.4 32.4 32.4 5.4
C2 [pF] 10.8 10.8 10.8 10.8 1.8
LF_CAP 3 3 3 3 0
R1 [k] 96 48 68 34 76
LF_RES1 7 2 4 1 5
R3 [k] 57 28 40 20 5
LF_RES3
8 3 5 2 0
Table 18. Internal Dual Path Filter Settings.
The design of the PLL filter will strongly affect the performance of the frequency synthesizer. Input parameters, when designing the loop filter for the MICRF405, are mainly the modulation method and the bit rate. Internal loop filter, which have relative
high bandwidths, is recommended for ASK. The external filter must be used when the bandwidth must be low. These choices will also affect the switching time and phase noise.
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Modulation
Adr A6..A0 0001011 0001110 0001111 0010000 0010001 0010010 D7 LowBatt_en=1 Mod_I4=0 VCO_Fr_Chk=0 MOD_TEST1=0 ASK_PN_en=0 ASKn1=1 D6 Freq_Band1=0 Mod_I3=1 VCO_Fr_Auto=0 Prescaler_Sel=0 ASK_EN=0 ASKn0=0 D5 Freq_Band0=1 Mod_I2=0 FSKn2=1 FSKClk_K5=1 ASKshape2=1 ASKClk_K5=1 D4 VCO_freq2=0 Mod_I1=0 FSKn1=0 FSKClk_K4=1 ASKshape1=1 ASKClk_K4=1 Data D3 VCO_freq1=1 Mod_I0=1 FSKn0=0 FSKClk_K3=0 ASKshape0=1 ASKClk_K3=0 D2 VCO_freq0=1 Mod_A2=0 Mod_F2=1 FSKClk_K2=1 ASK2=1 ASKClk_K2=1 D1 Modulation1=1 Mod_A1=1 Mod_F1=0 FSKClk_K1=0 ASK1=1 ASKClk_K1=0 D0 Modulation0=0 Mod_A0=1 Mod_F0=0 FSKClk_K0=0 ASK0=1 ASKClk_K0=0
The frequency modulation can be done in three different ways with the MICRF405, either by closed-, open loop VCO modulation or by modulation with the internal dividers. Amplitude modulation can also be done in two different ways, either ASK/OOK or Spread Spectrum ASKTM. All these different types of modulation is selected by Modulation1-0 and ASK_en (See chapter bit description for details). Closed loop VCO modulation (Modulation[1:0]=0), the modulation is applied directly to the VCO. The PLL will see the modulation as a frequency error and try to tune the VCO back to carrier. The PLL bandwidth therefore, needs to be sufficiently low enough not to cancel the modulation (at least 20 times lower than the slowest variation of the modulation). Also, the modulation needs to be DCfree, usually by encoding the data by a DC-free code such as Manchester or 3b4b. In most cases, an external PLL loop filter must be used to fulfill the demand for low bandwidth. Please see the Modulator section for details on deviation and shaping. Open Loop VCO Modulation (Modulation[1:0]=1), modulation is applied directly to the VCO. The VCO is now left free-running. The varactor voltage will now be stored on a large external capacitor connected to the VARIN pin and the PLL is disabled during the modulation. With the PLL disabled, the modulation will not be canceled and the modulated data signal may include DC-components. The switching between PLL active and disabled is done automatically by checking the DATAIN pin. If it is tristated the PLL is active, and if it is either high or low or transitioning between high or low the PLL is then disabled and the data on the DATAIN pin is transmitted. When data is transferred through the SPI the PLL is disabled during the transmission of a packet, while enabled else. In this mode, the PLL bandwidth can be fairly high as it is disabled during transmission. However, due to the large external capacitor, C3 in Figure 11b), the bandwidth is limited due to the pole created by this capacitor. Both internal with 56 phase margin and external filters April 2006 27
are suitable. A high quality capacitor of 10-47nF (COG type) should be connected on pin VARIN-toground to ensure minimum frequency drift due to leakage and frequency drift caused by the capacitor dielectric relaxation phenomenon (25kHz offset after 50ms). For deviation and shaping, please see the Modulator section. The frequency drift (Hz/ms) over temperature due to leakage is shown in Figure 12 with a 33nF COG external capacitor. Figure 13 shows the frequency drift in open loop VCO modulation due to capacitor dielectric relaxation. The drift is around 40kHz during a time period of 50ms. Of the 40kHz drift, 5-10kHz is due to an initial offset caused by the modulator itself.
IFB 10 MHz Ref
160k A
0 Hz
* Att
30 dB
AQT 100 ms
120k 1 AP CLRWR
80k
TRG
40k
0
-40k
-80k
-120k
-160k
-200k
-240k
Center 915.00004 MHz
10 ms/
Date: 11.JAN.2006
10:10:03
Figure 12. Frequency Drift Due to Capacitor Dielectric Relaxation at 915MHz.
M9999-041906 (408) 955-1690
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MICRF405 {PA[2:0]-ASK[2:0]}*3dB. If PA[2:0]<=ASK[2:0], the ASK modulation will be On Off Keying (OOK). For example, PA[2:0]=7 and ASK[2:0]=7 is OOK, but if ASK[2:0]=4, the modulation depth is -9dB (output power for "1" is 10dBm and "0" is 1dBm). The modulation depth is a tradeoff between occupied bandwidth and sensitivity in the receiver. When increasing the modulation depth, the pulling effect of the VCO will also increase and can be seen as FM components in the transmitted signal. To reject the pulling of the VCO, shaping can be applied to the ASK signal. The ASKshape[2:0] bits control the shaping, where ASKshape[2:0] = 7 gives the most shaping. The shaping is user selectable but a table of recommended values is shown in Table 19.
ASK bitrate (kbps) < 4.8 < 9.6 < 19.2 < 38.4 < 50 Recommended ASKshape 7 6 4 2 0
Openloop drift Vdd=3.6V
100 Frequency drift (Hz/ms) 0 -100 -200 -300 -400 -500 -600 -700 -40 -20 0 20 40 60 80 100 120 Temperature (degC)
Figure 13. Carrier Drift in Open-Loop Modulation.
Divider Modulation Modulation[1:0]=2, modulation by switching between two sets of dividers, A0/N0/M0 and A1/N1/M1, is selected. In this case, the PLL needs to settle at the new frequency for each bitshift. Therefore, the PLL bandwidth needs to be sufficiently high enough to follow the modulation. The PLL bandwidth/bit rate ratio controls the filtering of the modulation. A large ratio gives little filtering and a square shape to the data; while a small ratio gives hard filtering of the data. To avoid large overshoots, a large phase margin is desired, about 70 degrees will give about 10% overshoot. The tradeoff is less rejection of the phase detector frequency. ASK Modulation is selected when ASK_en=1 and Modulation[2:0]=3. The ASK modulation depth is controlled by the ASK[2:0] bits, and is equal to
Table 19. Recommended ASK Shaping.
A high PLL bandwidth will also help to avoid pulling of the VCO. The internal third order loop filter should be selected.
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* RBW 3 kHz
Ref
10
15 dBm
Att
50 dB
VBW 10 kHz SWT 70 ms
Marker 1 [T1 ] -23.62 dBm 915.018000000 MHz Delta 1 [T1 ] 4.58 dB -90.000000000 kHz
A
1 PK MAXH
0
D1 1 dBm
-10
1
-20
D2 -19 dBm
1
-30
-40
-50
-60
-70
-80
Center 915 MHz
60 kHz/
Span 600 kHz
Date: 27.MAR.2006
17:23:27
Figure 14. 33kbps, PA=6, ASK=7, ASKshape=2 (Fphd=2MHz, 209kHz internal loop filter). Spread Spectrum ASKTM is a combination of traditional ASK combined with FSK dithering. This modulation type goes under FCC part 15.247 digital modulation allowing higher output power without FHSS. The FSK dithering frequency, applied to the ASK signal, is greater than the ASK data rate and therefore, a traditional ASK/OOK receiver with
500kHz noise bandwidth can be used. FSK is applied using divider modulation Modulation[1:0]=2, due to the high loop filter bandwidth requirement of the ASK modulation. The ASK_PN_en signal controls whether the dithering is a "010101"-pattern, ASK_PN_en=0, or a "111101011001000"-pattern, ASK_PN_en=1.
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the better shaping of the signal. However in some cases, low FSKn causes the modulator to saturate (Please see the section Modulator for details). When Manchester encoding is enabled, Manchester_en=1, FSKn needs to bigger than zero for the modulator to operate properly. When sending ASK with FSK spreading, FSKClk_K and FSKn set the speed of the FSK spreading. The bit rate of the ASK is set similar with the two parameters ASKClk_K and ASKn. The relationship is now: BR = f XTAL ASKClk _ K 2 5+ ASKn (2)
Bit Rate Settings The bit rate is set separately for ASK and FSK modulation to support ASK modulation with FSK spreading. The FSK bit rate is set with the two parameters FSKClk_K and FSKn. The relationship is
BR =
f XTAL FSKClk _ K 2 3 +FSKn
(1)
where: BR: Bit rate. fXTAL: Crystal oscillator frequency. FSKClk_K: Integer in the range [1..63] (6 bit). FSKn: Integer in the range [0..5] (3 bit). A procedure to find the settings for the desired bit rate is described below: 1. Set FSKn to 0. 2. Calculate FSKClk_K by using this formula: f XTAL FSKClk _ K = BR 23+FSKn 3. If FSKClk_K is too high, increment FSKn by one, and then jump to 2. In some cases, several combinations of FSKClk_K and FSKn will give the bit rate. If VCO modulation is selected, Modulation[1:0] < 2, then the lower FSKn
Modulator
Adr A6..A0 0001110 0001111 0010000 D7 Mod_I4=0 VCO_Fr_Chk=0 MOD_TEST1=0 D6 Mod_I3=1 VCO_Fr_Auto=0 Prescaler_Sel=0 D5 Mod_I2=0 FSKn2=1 FSKClk_K5=1 D4 Mod_I1=0 FSKn1=0 FSKClk_K4=1
where the new parameters are: ASKClk_K: Integer in the range [1..63] (6 bits). ASKn: Integer in the range [0..3] (2 bits). A procedure for finding a bit rate will be equal to FSK, but with this formula:
BR 25+ ASKn Due to the high flexibility of the modulator, a brief explanation of how it works will ease the use of it. Figure 15 shows a block diagram of the components of the modulator.
ASKClk _ K =
f XTAL
Data D3 Mod_I0=1 FSKn0=0 FSKClk_K3=0 D2 Mod_A2=0 Mod_F2=1 FSKClk_K2=1 D1 Mod_A1=1 Mod_F1=0 FSKClk_K1=0 D0 Mod_A0=1 Mod_F0=0 FSKClk_K0=0
Figure 15. Modulator Block Diagram.
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Micrel The two first blocks are generating a clock for the modulator. This clock is, together with the user data, used to control a charge pump. The charge pump current is controlled by a DAC. Each time the input data changes state, a charge is then injected into the capacitor to generate a modulation signal. The charge magnitude is controlled by the charging current and by charging time (inversely proportional with modulator clock). To be able to achieve small deviations, it is possible to attenuate the modulation signal. Finally, the signal is filtered to narrow transmitter output spectrum. The procedure is first to determine the settings concerning the data bit rate, then, these values will be used in the calculation of the frequency deviation. Finally, the user must see if the desired values cause the modulator to saturate.
Deviation Setting Deviation controlled by user parameters FSKClk_K, MOD_I, and MOD_A, together with physical parameters fXTAL and KVCO. All user parameters can be set in software, and fXTAL (crystal oscillator frequency) is set when designing in the radio chip. KVCO (VCO gain) is a parameter of the radio chip, and is not controllable by the user. The crystal oscillator frequency, fXTAL, is divided by FSKClk_K to generate the modulator clock. Since this modulator clock is controlling the rise and fall times for the modulator, the frequency deviation is inversely proportional to this clock. The relationship is shown in equation (3):
MICRF405
Const2 54.7 fC: Carrier frequency of the radio. FreqBand: Frequency band. 0: 315MHz, 1: 433MHz and 2: 900MHz. In equation (5), it is evident that the VCO gain is dependent of carrier frequency. MOD_I is probably the best parameter to alter if counteracting this effect if necessary. Combining equations (3), (4), and (5) gives us an expression for the frequency deviation:
fDEV =
)) FSKClk_K MOD_ I Const + (Const fC (3 - FreqBand 1 2 3 - FreqBand fXTAL 2MOD_ A
(6)
Observe that equation (6) gives single-sideddeviation. Peak-to-peak deviation is twice this value.
Shaping The modulation waveform will be shaped due to the charging and discharging of a capacitor. The waveform looks like a Gaussian filtered signal with a BandwidthPeriod-product, BT, given by:
fDEV
FSKClk_K f XTAL
(3)
It is assumed that FSKClk_K will be constant for most applications to keep bit-rate and shaping constant, although this is not a requirement. The primary two controls of frequency deviation are MOD_I and MOD_A. Of these two, MOD_I is the parameter that controls the signal generation, while MOD_A controls attenuation of this signal. The reason for using an attenuator is to be able to generate small deviations at high values of FSKClk_K. The relationship is shown in equation (4).
BT = 2 FSKn (7) where: BT: Shaping factor. It is evident from this that a low FSKn gives a low shaping factor, and is thus preferred if it is possible to choose FSKn freely. In addition to this, it is possible to smooth the modulator output in a programmable low-pass filter. This filter is controlled by the parameter MOD_F. The parameter should be set according to equation (8). MOD _ F 150 x 10 3 BR (8)
2 MOD _ A Finally, the VCO gain is given by equation (5). KVCO = where: Const1 - 30.6324 x 10 9
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fDEV
MOD _ I
(4)
Modulator Saturation The modulator output voltage is generated by a capacitor that is being charged. This means that there is a risk of saturating the modulator if the charge received by the capacitor is too large. Use equation (9) to determine the maximum value of MOD_I that can be used.
Const 1 + (Const 2 fC (3 - FreqBand )) (5) 3 - FreqBand
f XTAL -6 MOD _ I FSKClk_K 28 x 10 + 1
(9)
If it turns out that the MOD_I-range is too small for your requirements, try increasing FSKn and decreasing FSKClk_K accordingly.
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Lock Detect
Adr A6..A0 0001100 0001111 D7 LowBatt_level=0 VCO_Fr_Chk=0 D6 LDO_by=0 VCO_Fr_Auto=0 D5 LDO_en1=1 FSKn2=1 D4 LDO_en0=1 FSKn1=0 Data D3 MOD_LDc_en=0 FSKn0=0 D2 PA_FEc_en=0 Mod_F2=1 D1 PA_LDc_en=0 Mod_F1=0 D0 LD_en=1 Mod_F0=0
The lock detector can be enabled by setting LD_en=1. When pin LD is high, it indicates that the PLL is in lock. Care must be taken when monitoring the LD during data transmission using the closed loop modulation. Due to the fact that the PLL tries to cancel the modulation signal, there will be some PLL activity during the transmission time, especially when the PLL BW is too high relative to the bitrate. The LD may therefore, show that the PLL is not in lock. When starting a transmit session, the LD signal is helpful in deciding when to turn on the PA. When going from power down or stand by mode to TX mode, or after a frequency change, the PLL needs some time to lock on to the frequency. During this time it is necessary to keep the PA off. This is done by setting PA[2:0]=0 and PA_LDc_en=0. When the LD signal goes high, it is safe to turn on the PA, by setting the PA[2:0] to the desired output level. Depending on the output power, and the loop filter, the LD signal might drop during start up of the PA due to VCO pulling. When LD is high again it is time to start the modulation. The lock detect signal is used internally in several functions; the VCO_Fr_Chk/Auto, the MOD_LDc and the PA_LDc. The VCO_Fr_Chk/Auto are described in detail under the VCO chapter. PA_LDc (PA Lock Detect Control) is used to automatically turn on the PA the moment the PLL has locked on to the frequency. This function is enabled when the PA_LDc_en bit is set. From power down or stand by, simply program the MICRF405 to TX with the wanted PA output setting. The MICRF405 will then automatically turn on the PA
once the PLL has locked. The PA will remain on until PA[2:0]=PA_LDc_en=0 or the transmitter leaves transmit mode (Mode[1:0]<>3). However, the PA is temporary turned off for every internal load pulse or if the DATAIN pin is tri-stated in open loop modulation (Modulation[1:0]=2). This means that if you want to change frequency, the PA will shut off during the settling of the new frequency, and then it is turned on once the PLL has locked on to the new frequency. It is necessary that LD_en is set for the PA_LDc function to work. The correct time to start modulation will be internally decided when the MOD_LDc (Modulation Lock Detect control) bit is set. This function is only working when data is transferred through the SPI (Bit_IO_en=0). The phase detector frequency (Fphd) has to be < 200kHz when MOD_LDc is enabled. Program the MICRF405 in transmit at the proper output frequency and power strength. Then, write the frame length of the packet into the data buffer. The MICRF405 will now delay the modulation until the PLL has locked with PA turned on. For this function to work, both LD_en and PA_LDc_en must be set. This function is especially useful when transmitting several packets without leaving the TX mode and the PA_FEc_en bit is set. After a packet is finished transmitted, the PA_FEc function will turn the PA off until a new packet is to be sent. If the MOD_LDc function is not enabled, the modulation and turning on the PA will then start simultaneously, there by creating distorted start of packet and interfering with the settling of the PLL due to PA turn on. With MOD_LDc enabled the modulation will be delay until the PLL has locked with PA on.
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Low Dropout Regulator (LDO) and Low Battery Detector
Adr A6..A0 0001011 0001100 D7 LowBatt_en=1 LowBatt_level=0 D6 Freq_Band1=0 LDO_by=0 D5 Freq_Band0=1 LDO_en1=1 D4 VCO_freq2=0 LDO_en0=1 Data D3 VCO_freq1=1 MOD_LDc_en=0 D2 VCO_freq0=1 PA_FEc_en=0 D1 Modulation1=1 PA_LDc_en=0 D0 Modulation0=0 LD_en=1
The MICRF405 has three internal LDOs powering up different parts of the circuit, as can be seen in the Block Diagram. The output voltages of the LDOs are around 2.4V. The LDOs can be turned off (default setting is on) by setting the LDO_en[1:0]=0. When LDO_en[1:0]=3, the power supply range is 2.2-3.6 volt. Power must be applied to pin 1 and 11. A capacitor is needed on each of the LDO output for stability (pin 3, 9 and 23). In sleep mode, all the LDOs are turned off. The interface and control blocks run on unregulated power, meaning that the register content will be kept and that the programming can also be done in this mode. An option, where the LDOs are bypassed, is enabled by setting the LDO_by bit, and when activated, the transmitter can operate at 2.2V-2.5V. Since the LDO drop is decreased, the output power is slightly higher. However, in this mode it is of vital importance that the input power is below 2.5V as the pass devices in the LDOs are fully on and not regulated. It is recommended that this option is used in combination with the low battery detector. When LDO_en[1:0]=0, the power supply range is 2.2-2.5 volt. Power must be applied to pin 1, 3, 9, 11 and 23. Capacitors are now only needed for normal
noise decoupling. Alternatively, connect power to pins 1 and 11 only, and set LDO[1:0]=3 and LDO_by=0. The LDOs are controlled with 2 bits, enabling the option of running the complete circuit on the RF LDO alone (LDO_en[1:0]=1), or on the RF LDO and analog LDO (LDO_en[1:0]=2). Doing so, regulated power on the RFVDD pin must be externally routed to the AVDD and DVDD pin in the first case and, and from the RFVDD to the DVDD pin in the second case. These modes will save one or two of the external capacitors used for stabilizing the LDOs, but might influence the phase noise and spurious performance. Recommended use is therefore, LDO_en[1:0]=3 or 0. The low battery detector circuit is turned on when the LowBatt_en bit is set. It will monitor the voltage of the input power, pin 11, in standby and TX modes. If LDO_by=0, it will set the LowBatt interrupt if the voltages falls below 2.1V for LowBatt_level=1 and 2.0V for LowBatt_level=0. If LDO_by=1, it sets the interrupt when the voltages is below 1.9V/1.8V for LowBatt_level=1/0.
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Bit Description
Adr A6..A0 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 D7 Mode1=0 N0_7=0 M0_7=0 N1_7=0 M1_7=0 LowBatt_en=1 LowBatt_level=0 Bit_IO_en=1 Mod_I4=0 VCO_Fr_Chk=0 `0' ASK_PN_en=0 ASKn1=1 INT_LF_EN=1 LF_High_PM=1 ClkOut_1=0 INT_LF_TEST=0 PA_IB3=1 VCO_freq_O2 SyncID3_7=1 SyncID2_7=1 SyncID1_7=1 SyncID0_7=1 DATA_7 D6 Mode0=1 N0_6=1 M0_6=0 N1_6=1 M1_6=0 Freq_Band1=0 LDO_by=0 Manchester_en=0 Mod_I3=1 VCO_Fr_Auto=0 Prescaler_Sel=0 ASK_EN=0 ASKn0=0 CP_CUR1=0 LF_CAP1=1 ClkOut_0=0 VCO_IB2=0 PA_IB2 =0 VCO_freq_O1 SyncID3_6=1 SyncID2_6=1 SyncID1_6=1 SyncID0_6=1 DATA_6 D5 PA2=1 A0_5=0 N0_5=1 M0_5=1 A1_5=0 N1_5=1 M1_5=1 Freq_Band0=1 LDO_en1=1 Sel_CRC1=1 Mod_I2=0 FSKn2=1 FSKClk_K5=1 ASKshape2=1 ASKClk_K5=1 CP_CUR0=1 LF_CAP0=1 XCO_Fast=1 VCO_IB1=0 PA_IB1=0 VCO_freq_O0 SyncID3_5=1 SyncID2_5=1 SyncID1_5=1 SyncID0_5=1 DATA_5 SyncID3_4=0 SyncID2_4=0 SyncID1_4=0 SyncID0_4=0 DATA_4 SyncID3_3=0 SyncID2_3=0 SyncID1_3=0 SyncID0_3=0 DATA_3 D4 PA1=1 A0_4=0 N0_4=1 M0_4=0 A1_4=1 N1_4=0 M1_4=0 VCO_freq2=0 LDO_en0=1 Sel_CRC0=1 Mod_I1=0 FSKn1=0 FSKClk_K4=1 ASKshape1=1 ASKClk_K4=1 LF_RES1_4=0 LF_RES3_4=0 XCOtune4=1 VCO_IB0=0 PA_IB0=1 Data D3 PA0=1 A0_3=1 N0_11=0 N0_3=0 M0_11=0 M0_3=0 A1_3=1 N1_11=0 N1_3=1 M1_11=0 M1_3=0 VCO_freq1=1 MOD_LDc_en=0 SyncID_Len1=0 Mod_I0=1 FSKn0=0 FSKClk_K3=0 ASKshape0=1 ASKClk_K3=0 LF_RES1_3=1 LF_RES3_3=0 XCOtune3=0 VCO_by=0 PAB_IB3=1 D2 ClkOut_en=1 A0_2=1 N0_10=0 N0_2=0 M0_10=0 M0_2=0 A1_2=1 N1_10=0 N1_2=1 M1_10=0 M1_2=0 VCO_freq0=1 PA_FEc_en=0 SyncID_Len0=1 Mod_A2=0 Mod_F2=1 FSKClk_K2=1 ASK2=1 ASKClk_K2=1 LF_RES1_2=0 LF_RES3_2=1 XCOtune2=0 OUTS2=0 PAB_IB2=0 VC_HI SyncID3_2=1 SyncID2_2=1 SyncID1_2=1 SyncID0_2=1 DATA_2 D1 Sync_en=1 A0_1=1 N0_9=0 N0_1=1 M0_9=0 M0_1=0 A1_1=1 N1_9=0 N1_1=1 M1_9=0 M1_1=0 Modulation1=1 PA_LDc_en=0 Pream_Len1=1 Mod_A1=1 Mod_F1=0 FSKClk_K1=0 ASK1=1 ASKClk_K1=0 LF_RES1_1=0 LF_RES3_1=0 XCOtune1=0 OUTS1=0 PAB_IB1=0 VC_LO SyncID3_1=0 SyncID2_1=0 SyncID1_1=0 SyncID0_1=0 DATA_1 D0 Load_en=1 A0_0=0 N0_8=0 N0_0=1 M0_8=0 M0_0=1 A1_0=1 N1_8=0 N1_0=1 M1_8=0 M1_0=0 Modulation0=0 LD_en=1 Pream_Len0=0 Mod_A0=1 Mod_F0=0 FSKClk_K0=0 ASK0=1 ASKClk_K0=0 LF_RES1_0=1 LF_RES3_0=1 XCOtune0=0 OUTS0=0 PAB_IB0=1 LOW_BATT SyncID3_0=1 SyncID2_0=1 SyncID1_0=1 SyncID0_0=1 DATA_0
The 5 last bytes (0011001-0011101) are valid instantly, in other words, no load pulse (raising SEN) is needed to activate the changes.
Mode1 0 0 1 1 Mode0 0 1 0 1 State Power down Standby Transmit mode Table 20. Main Mode. Comments Keeps Register configuration Crystal Oscillator running Transmit mode
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PA2 0 0 0 0 1 1 1 1
PA1 0 0 1 1 0 0 1 1
PA0 0 1 0 1 0 1 0 1
State 21dB attenuation or PA off if PA_LDc_en=0 18dB attenuation 15dB attenuation 12dB attenuation 9dB attenuation 6dB attenuation 3dB attenuation Max output Table 21. Power Amplifier.
ClkOut_en 0 1 1 1 1
ClkOut_1 X 0 0 1 1
ClkOut_0 X 0 1 0 1
State CLKOUT off CLKOUT on CLKOUT on CLKOUT on CLKOUT on Table 22. Output Clock.
Comments Output is 0 volt. The XCO frequency is divided by 16. The XCO frequency is divided by 8. The XCO frequency is divided by 4. The XCO frequency is divided by 2.
Bit_IO_en 0 1 1
Sync_en X 0 1
State DCLK pin on, RDY DCLK pin off DCLK pin on, DATACLK
Comments Byte ready, RDY, signal from databyte Transparent transmission of data Bit-clock is generated by transmitter Table 23. Synchronizer Mode
ASK_EN 0 0 0 0 1 1 1 1
Modulation1 0 0 1 1 0 0 1 1
Modulation0 0 1 0 1 0 1 0 1
State Closed loop VCO-modulation Open loop VCO-modulation Modulation by A,M and N Not used ASK modulation with spreading code applied to VCO. Not recommended. ASK modulation with spreading code applied to VCO. Not recommended. ASK modulation with spreading code applied to internal modulation by A, M and M ASK modulation Table 24. Modulation.
Comments VCO is phase-locked VCO is free-running Modulation inside PLL
VCO is phase-locked VCO is free-running Modulation inside PLL VCO is phase-locked
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ASK2 0 0 0 0 1 1 1 1
ASK1 0 0 1 1 0 0 1 1
ASK0 0 1 0 1 0 1 0 1
State 3dB ASK depth 6dB ASK depth 9dB ASK depth 12dB ASK depth 15dB ASK depth 18dB ASK depth 21dB ASK depth > 30dB ASK depth
Table 25. ASK Modulation Depth When PA[2:0]=7. ASKshape 0..7 Comments Programmable ASK filter. It can be programmed in eight steps. "0" is no shaping, "7" most shaping. Table 26. ASK Shaping/Filtering. XCOtune 0..31 Comments Programmable XCO load capacitor Table 27. XCO Capacitor Setting. XCO_Fast 0 1 Comments The XCO is running on a constant bias current. When going from PD to TX mode, the XCO is running on a high current during start up. Table 28. XCO Fast Startup. Low_Batt_en 0 1 1 1 1 LowBatt_level X 0 1 0 1 LDO_by X 0 0 1 1 Comments Low battery detect circuit off Low battery detect circuit active. Interrupt is flagged if VDD falls below 2V. Low battery detect circuit active. Interrupt is flagged if VDD falls below 2.1V. Low battery detect circuit active. Interrupt is flagged if VDD falls below 1.8V. Low battery detect circuit active. Interrupt is flagged if VDD falls below 1.9V. Table 29. Low Battery Detect.
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MICRF405
LDO_by X 1 0 0 0
LDO_EN1 0 X 0 1 1
LDO_EN0 0 X 1 0 1
Comments LDOs turned off, power applied to AVDD, DVDD, RFVDD, min/max is 2.0/2.5 V, and to VDD pin 11 and 1, min/max is 2.0/3.6V. LDOs bypassed, power applied to the VDD pin1 and VDD pin11, min/max is 2.0/2.5 V PA LDO turned on, power applied to VDD pin1 and 11, min/max is 2.0/3.6V, and to AVDD and DVDD, min/max is 2.0/2.5V PA and AVDD LDO turned on, power applied to the VDD pin1 and 11, min/max is 2.0/3.6V, and to DVDD, min/max is 2.0/2.5V PA, AVDD and DIG LDO turned on, power applied to the VDD pin1 and VDD pin 11, min/max is 2.0/3.6V Table 30. Low DropOut Voltage Regulator.
PA_LDc_en 0 1
Comments PA is only controlled by Mode1 and Mode and PA0-2, PA on in transmit mode (Mode[1:0]=3 and PA[2:0]>0) In transmit mode, PA is turned on by Lock Detect (LD=1 -> PA on). PA is turned off by load pulse or when using openloop modulation and setting the DATAIN pin in tri-state. PA will be turned on again once LD goes high again. LD_en must be set to 1. Table 31. Lock Detect Controlled PA.
MOD_LDc_en 0 1
Comments Modulation starts once frame length is written into data byte. Modulation starts once frame length is written into data byte and PA is turned on and LD is high. Table 32. Lock Detect Controlled Start of Modulation (only for BIT_IO_en=0).
PA_FEc_en 0 1
Comments PA is turned off by Mode1 and Mode0 or PA0-2 and PA_LDc_en=0 PA is turned off immediately after the frame is transmitted. Table 33. Frameend Controlled PA.
LD_en 0 1
State LD off LD on
Comments Output is 0 volt, or test signals specified by OUTS[2:0] LD pin high indicate that the PLL is locked Table 34. Lock Detector.
SyncID_Len1 0 0 1 1
SyncID_Len0 0 1 0 1
Comments SyncID length is 1 byte. SyncID0 is sent SyncID length is 2 bytes. SyncID0 and SyncID1 is sent SyncID length is 3 bytes. SyncID0, SyncID1 and SyncID2 is sent SyncID length is 4 bytes. SyncID0, SyncID1, SyncID2 and SyncID3 is sent. Table 35. SyncID Field Length.
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MICRF405
Pream_Len1 0 0 1 1
Pream_Len0 0 1 0 1
Comments Preamble length is 1 byte. Preamble length is 2 bytes. Preamble length is 3 bytes. Preamble length is 4 bytes. Table 36. Preamble Field Length.
Sel_CRC1 0 1 1
Sel_CRC0 X 0 1
Comments CRC disabled CCITT-8 CRC enabled. Byte is sent after payload data. Polynomial function: X^8+X^5+X^4+1. (Byte part of Frame Length) ITU-16 CRC enabled. Bytes are sent after payload data. Polynomial function: X^16+X^12+X^5+1. (Byte part of Frame Length) Table 37. CRC Select.
Manchester_en 0 1
Comments Manchester encoding disabled. Manchester encoding enabled. Data will be encoded before transmitted. FSKn > 0 when using modulator. Table 38. Manchester Encoding (only when BIT_IO_en=0).
VCO_freq2 VCO_freq1 VCO_freq0 Comments 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Table 39. VCO Frequency. MOD_I 1..31 Comments The deviation is linearly dependent of MOD_I Table 40. Modulator Current Setting for Frequency Deviation. MOD_A 0..4 Comments Frequency deviation attenuator (or range selector). The attenuations are (values 0 through 4, respectively) 1 1 ,1 2 ,1 4 ,1 8 and 1 16 950MHz, 315MHz 915 MHz 868 MHz, 433MHz Not used
Table 41. Modulator Attenuator Setting for Frequency Deviation.
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MICRF405
MOD_F 0..3
Comments Programmable smoothing filter after attenuator. This can be programmed in four steps, and will produce reasonable results for the highest bit rates. Table 42. Modulator Filter Setting.
FSKn 0..5
Comments The bit rate clock is set by dividing the crystal oscillator frequency by FSKClk_K*2^(3+FSKn). Table 43. Bit Rate Setting.
FSKClk_K 1..63
Comments The crystal oscillator is divided by this number to produce modulator clock and it is divided further down by 2^(3+FSKn) to produce the bit rate clock. Table 44. Modulator and Bit Rate Clock Setting.
ASKn 0..3
Comments The ASK bitrate clock is set by dividing the crystal oscillator frequency by ASKClk_K*2^(5+ASKn) Table 45. Bit Rate Setting.
ASKClk_K 1..63
Comments The crystal oscillator is divided by this number and is divided further down by 2^(5+ASKn) to produce the ASK bitrate clock. Table 46. Modulator and Bit Rate Clock Setting.
ASK_PN_en 0 1
Comments 01010101...pattern is used in the FSK spreader during ASK. 111101011001000 repeated pattern is used in the FSK spreader during ASK. Table 47. ASK Spreading.
VCO_IB2 1 1 0 0
VCO_IB1 1 0 1 0
VCO_IB0 1 1 1 0
Comments Bias setting for VCO_Freq=0/1, 860 MHz Bias setting for VCO_Freq=2/3, 868 MHz Bias setting for VCO_Freq=4/5, 915 MHz Bias setting for VCO_Freq=6/7, 950 MHz (**) Table 48. VCO Bias Bit.
(**): When VCO_IB=000b, the bias current is set automatically by the two VCO_freq bit.
VCO_by 0 1
State VCO is active VCO is bypassed
Comment When VCO is bypassed, a differential signal can be applied to the circuit using pin CPOUT and VARIN Table 49. VCO Bypass Bit.
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MICRF405
OutS2 0 0 0 0 1 1 1 1
OutS1 0 0 1 1 0 0 1 1
OutS0 0 1 0 1 0 1 0 1
The signals are available on the LD output Gnd N-div M-div ModOut Bandgap DVDD TXSYMBOL - output of packet handling engine
Table 50. Test Signals. Only Available When LD_en=0.
PA_IB3 0 0 1 1 PA_IB1 0 0 1 1 0 0 1 1 0 0 1 1
PA_IB2 0 1 0 1 PA_IB0 0 1 0 1 0 1 0 1 0 1 0 1
State PA uses bias current from PTAT bias source, external resistor (Pin 6) PA uses bias current from CI bias source, external resistor (Pin 24) PA uses bias current from internal bias source, PTAT PA uses bias current from internal bias source, PTAT + CI State PA bias current setting, lowest bias current PA bias current setting PA bias current setting PA bias current setting, highest bias current State PAbuffer uses bias current from PTAT bias source, external resistor (Pin 6) PAbuffer uses bias current from CI bias source, external resistor (Pin 24) PAbuffer uses bias current from internal bias source, PTAT PAbuffer uses bias current from internal bias source, PTAT + CI State PAbuffer bias current setting, lowest bias current PAbuffer bias current setting PAbuffer bias current setting PAbuffer bias current setting, highest bias current Table 51. PA and PAbuffer Bias Current Setting. Max. achievable Phase Margin 57 57 57 57 69 69 69
PAB_IB3 PAB_IB2
PAB_IB1 PAB_IB0
LF_High_PM X 0 0 0 1 1 1
LF_CAP1 0 0 1 1 0 1 1
LF_CAP0 0 1 0 1 1 0 1
C1 5.4pF 10.8pF 21.6pF 32.4pF 10.8pF 21.6pF 32.4pF
C2 1.8pF 3.6pF 7.2pF 10.8pF 1.8pF 3.6pF 5.4pF
Table 52. Loop Filter Capacitors Values.
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MICRF405
LF_RES1<4:0> LF_RES3<4:0>
R1 (k)
R3 (k)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
24.1 34.3 44.5 54.7 64.9 75.1 85.3 95.5 105.7 115.9 126.1 136.3 146.5 156.7 166.9 177.1 187.3 197.5 207.7 217.9 228.1 238.3 248.5 258.7 268.9 279.1 289.3 299.5 309.7 319.9 330.1 340.4
Table 53. Loop Filter Resistor Values.
5.9 12.3 18.7 25.1 31.5 37.9 44.3 50.7 57.1 63.5 69.9 76.3 82.7 89.1 95.5 101.9 108.3 114.7 121.1 127.5 133.9 140.3 146.7 153.0 159.4 165.8 172.2 178.6 185.0 191.4 197.8 204.2
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M9999-041906 (408) 955-1690
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MICRF405
Typical Application Circuit
Figure 16. Typical Application Circuit
Bill of Materials
FSK/ASK 915MHz Item
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Part
C1 C2 C4 C5 C6 C10 C12 C13 C14 C16 C17 R1 R5 L1 L2 Y1
Value
3p3 100pF 3p3 100nF 10nF 100nF 100nF 100nF 10nF 82k 10nH 12nH 16MHz
Description
See Table 17 See Table 17 Capacitor, 0603, 0.25pF, COG, 50V, -55,+125C Capacitor, 0603, 5%, COG, 50V, -55,+85C Capacitor, 0603, 0.25pF, COG, 50V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 50V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 50V, -55,+125C See Table 17 Resistor, 0603, 1%, 50V, -55,+125C Inductor, 0603, 5%, -40,+125C Inductor, 0603, 5%, -40,+125C Crystal, TSX-10A, 10ppm, -20,+75Cl
Manufacturer
Part Number
Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Coilcraft Coilcraft Toyocom
CM105CG3R3C50A CM105CG101J50A CM105CG3R3C50A CM105X7R104K16A CM105X7R103K50A CM105X7R104K16A CM105X7R104K16A CM105X7R104K16A CM105X7R103K50A CR10-8202F 0603CS-10NXJB 0603CS-12NXJB TN4-26011
April 2006
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M9999-041906 (408) 955-1690
Micrel
MICRF405
FSK/ASK 868MHz Item
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Part
C1 C2 C4 C5 C6 C10 C12 C13 C14 C16 C17 R1 R5 L1 L2 Y1
Value
3p9 15pF 6p8 100nF 10nF 100nF 100nF 100nF 10nF 82k 10nH 12nH 16MHz
Description
See Table 17 See Table 17 Capacitor, 0603, 0.25pF, COG, 50V, -55,+125C Capacitor, 0603, 5%, COG, 50V, -55,+85C Capacitor, 0603, 0,5pF, COG, 50V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 50V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 50V, -55,+125C See Table 17 Resistor, 0603, 1%, 50V, -55,+125C Inductor, 0603, 5%, -40,+125C Inductor, 0603, 5%, -40,+125C Crystal, TSX-10A, 10ppm, -20,+75Cl
Manufacturer
Part Number
Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Coilcraft Coilcraft Toyocom
CM105CG3R9C50A CM105CG150J50A CM105CG6R8D50A CM105X7R104K16A CM105X7R103K50A CM105X7R104K16A CM105X7R104K16A CM105X7R104K16A CM105X7R103K50A CR10-8202F 0603CS-10NXJB 0603CS-12NXJB TN4-26011
FSK/ASK 433MHz Item
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Part
C1 C2 C4 C5 C6 C10 C12 C13 C14 C16 C17 R1 R5 L1 L2 Y1
Value
5p6 6p8 6p8 100nF 10nF 100nF 100nF 100nF 10nF 82k 47nH 47nH 16MHz
Description
See Table 17 See Table 17 Capacitor, 0603, 0,5pF COG, 50V, -55,+125C Capacitor, 0603, 0,5pF, COG, 50V, -55,+85C Capacitor, 0603, 0,5pF, COG, 50V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 50V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 50V, -55,+125C See Table 17 Resistor, 0603, 1%, 50V, -55,+125C Inductor, 0603, 5%, -40,+125C Inductor, 0603, 5%, -40,+125C Crystal, TSX-10A, 10ppm, -20,+75Cl
Manufacturer
Part Number
Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Coilcraft Coilcraft Toyocom
CM105CG5R6D50A CM105CG6R8D50A CM105CG6R8D50A CM105X7R104K16A CM105X7R103K50A CM105X7R104K16A CM105X7R104K16A CM105X7R104K16A CM105X7R103K50A CR10-8202F 0603CS-47NXJB 0603CS-47NXJB TN4-26011
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M9999-041906 (408) 955-1690
Micrel
MICRF405
FSK/ASK 315MHz Item
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Part
C1 C2 C4 C5 C6 C10 C12 C13 C14 C16 C17 R1 R5 L1 L2 Y1
Value
10p 100pF 10p 100nF 10nF 100nF 100nF 100nF 10nF 82k 47nH 47nH 16MHz
Description
See Table 17 See Table 17 Capacitor, 0603, 5%, COG, 50V, -55,+125C Capacitor, 0603, 5%, COG, 50V, -55,+85C Capacitor, 0603, 5%, COG, 50V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 50V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 16V, -55,+125C Capacitor, 0603, 10%, X7R, 50V, -55,+125C See Table 17 Resistor, 0603, 1%, 50V, -55,+125C Inductor, 0603, 5%, -40,+125C Inductor, 0603, 5%, -40,+125C Crystal, TSX-10A, 10ppm, -20,+75Cl
Manufacturer
Part Number
Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Kyocera Coilcraft Coilcraft Toyocom
CM105CG100J50A CM105CG101J50A CM105CG100J50A CM105X7R104K16A CM105X7R103K50A CM105X7R104K16A CM105X7R104K16A CM105X7R104K16A CM105X7R103K50A CR10-8202F 0603CS-47NXJB 0603CS-47NXJB TN4-26011
April 2006
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M9999-041906 (408) 955-1690
Micrel
MICRF405
Package Information
24-Lead MLF(R) (ML)
MLF 4 4x4mm Land pattern E Min 0.50 X1 0.30 Y1 0.70 C1 3.90 C2 3.90 X2 2.55 Y2 2.55
(R)
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M9999-041906 (408) 955-1690
Micrel
MICRF405
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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M9999-041906 (408) 955-1690

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